Announcements

CENG 3151: Lab for Computer Architecture

Semester: Fall 2025

Instructor: Zhichao Liu, Ph.D.

• Office: Delta Building, D-110
• Office Phone: 281-283-3833
• Email: LiuZ@UHCL.edu
• Office Hours: Tu. 10:30AM- 12:30PM Th. 10:30AM- 1:30PM

TA: TBD

• Email: TBD
• Office Hours: TBD

Meeting Time

• Sec. 01: Tu. 1:00 PM -3:50 PM
• Sec. 02: TBD Th. 1:00 PM -3:50 PM

Location: TBD

Course Description:

The course objective is to supplement CENG 3351 lectures with hands-on lab experience. Learning outcome is that each student completes a set of experiments using breadboard (NI Elvis), Multisim and VHDL that complement the material covered in the lecture.

Learning Outcomes:

• Students will simulate combinational circuit designs using Xilinx Vivado and VHDL.
• Students will implement combinational circuit designs using small scale, medium scale, and very large-scale integrated circuits.
• Students will adapt/modify their designs when preferred components are unavailable.
• Students will test implementations to show correct operation as per the design.
• Students will troubleshoot circuit designs functionality problems.
• Students will simulate synchronous and asynchronous sequential circuits using VHDL.
• Students will design an experiment that will determine the operations of a 32-bit ALU.

Course Schedule (Tentative):

Week	Topic	Due Date	Note	Recording	Submission Link
HW0 August 26	Introduction & Lab 0. Overview of Xilinx Vivado and VHDL Combinational Circuit Design (Warm Up exercise)	September 2
HW1 September 2	Lab 1. Combinational Circuit Design	September 9
HW2 September 9	Lab 2. Moore Sequential Circuit Design	September 16
HW3 September 16	Lab 3. Mealy Circuit Design	September 23
HW4 September 23	Lab 4. 4-bit full adder (Structural Model) Design	September 30
HW5 September 30	Lab 5. Data Register and Instruction Register Design	October 7
HW6 October 7	Lab 6. Memory Design RAM	October 14
HW7 October 14	Lab 7. Memory Design ROM	October 21
HW9 October 28	Lab 9. Design of a 32-bit Shifter	November 4
HW10 November 4	Lab 10. Binary Counter Design	November 11
HW11 November 11	Final Project – Part 1	November 26
HW12 November 18	Continue Final Project – Part 2	November 26

Late Submissions:

You are allowed to turn in one lab up to 3 days late without any penalty.
NOTE: late submission allowance cannot be used to turn in the Final Project.
After the student has exhausted this late submission allowance. Late submissions will penaltied with a deduction of 20 points for each day of delay (i.e., A minimum of 20 point will be deducted from the submitted work for each day or delay).

Grading Policy:

• Lab reports: 60%
• Pre-labs: 10%
• Project: 20%
• Attendance: 10%
• Total: 100%